1. Field of the Invention
The invention relates to a semiconductor structure and a layout structure for memory devices, and more particularly, to a semiconductor structure and a layout structure for flash memory devices.
2. Description of the Prior Art
Semiconductor memory has become increasingly popular for used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices. Electrically erasable programmable read only memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
With rapid advancement of semiconductor fabricating technology and miniaturization of the devices, more and more challenges have been emerged. For example, a conventional flash memory cell includes a memory gate and a select gate adjacent to the memory gate. With the shrink of the device size and of the process window, device performance becomes more and more susceptible to the misalignment between the select gate and the contact plugs. The memory devices are even failed because of the misalignment issue. Furthermore, when a spacer-typed select gate approach is adopted, the select gate includes a sloped profile and thus the contact plug, which must be infallibly landed on the spacer-typed select gate, may not physically contacts the select gate and thus adversely impacts the reliability.